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V-by-One® HS IP core |
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V-by-One® HS IP
core
V-by-One®HS是經由Thine Electronics
Inc. 發展而成支援更高速以及更高度被更好的FPD技術所需求的解決方案,同時也能降低開銷及上市時間。
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Scalable from 1 to 32 lanes
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Selectable color depth from 18 to 36bpp
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Auto pixel clock recovery
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Altera Video IP suite compatible.
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DisplayPort Receiver IP
core |
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DisplayPort
Receiver IP core
DisplayPort預示著一個在視訊連接上新的選擇。這是被產業龍頭(Intel,
DELL, Apple
etc)設計用來達成更低花費的直接驅動顯示器。DisplayPort不會被許可證和專利費用所阻礙。
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Support for 1,2 & 4-lane
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Support 1.62 & 2.7GB/s link rate
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80B/10B Decoder
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16-bit de-scrambler
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6,8,10,12 & 16 bit color support
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h.264 AVC Encoders from
Jointwave |
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h.264 AVC
Encoders from Jointwave
從Jointwave而來的h.264
編碼器優秀的效能家族。
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Input: Hsync Vsync 16bits parallel data, YUV4:2:2
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Output: NAL standard packets
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GOP configuration: I, IP
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I16x16 and I4x4 all intra prediction modes
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Multiple inter prediction modes
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CABAC or CAVLC entropy encoding
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Output bit rate: 0.5Mbps to 300Mbps
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1/4 sub-pixel motion estimation
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Mode Decision in 1/4 sub-pixel to get best quality
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Hadmard transform for intra and inter prediction
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Deblocking filter
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External memory: SDRAM/DDR/DDR2
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No external memory required for Intra Profile
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Cyclone III SDALTEVK Kit |
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Cyclone III
SDALTEVK Kit
對於3G SDI 專業視訊發展器花費節約的工具組。
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HSMC DUAL-LINK DVI Board |
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HSMC DUAL-LINK
DVI Board
Two
channel Dual-Link DVI output board for Altera FPGA
development kits with HSMC expansion port.
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Single link operation from 25-165 Megapixels per second
(VGA to UXGA)
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Dual link operation up to 330 Megapixels per second
(3200×2400)
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EDID reading/writing
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12-bit (½ pixel) DDR input with flexible input clocking:
Single-clock/dual-edge or dual-clock/single-edge
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I2C slave programming interface
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Cable distance support: Over 10 m
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Monitor detection through Hot-Plug
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Compliant with DVI 1.0
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Alera
Cyclone III Development Kit |
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1.Cyclone III Video Development Kit(使用EP3C120F780主板和HSMC擴充子板) |
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Cost effective kit targeted at
Video processing development using a Cyclone III device.
Cyclone III Video Development Kit :
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Altera EP3C120F780 Development
board
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HSMC Quad Video daughter
card
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HSMC DVI daughter card
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Collection of video reference
designs
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2.HSMC Broadcast Video Board |
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Develop profesional video fpga
based systems using the Bitec BVDC.
HSMC Broadcast Video Board :
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Dual ASI/SD-SDI
transmitter/receiver
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Adaptive cable equalizers
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Multi-rate cable drivers
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27 Mhz VCXO
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200Mhz Quadrature Modulating
14-bit DAC
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Flexible clocking options for
DAC
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3.HSMC Quad Video Board |
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Connect multiple live video
streams to your Altera FPGA using the Bitec Quad Video
board. Allows 4 S-Video or 8 Composite video inputs. An
integrated video output provides DVI, RGB or composite TV
connectivity.
HSMC Quad
Video Board :
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Four Separate Video Decoder
Channels accept NTSC (M, 4.43), PAL (B, D, G, H, I, M, N),
and SECAM (B, D, G, K, K1, L)
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Support ITU-R BT.601
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High-Speed 9-Bit ADC on each
channel
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Two Composite Inputs or One
S-video Input (for Each Channel)
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Brightness, Contrast,
Saturation, Hue, and Sharpness Control Through i2c
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Four Independent Polymorphic
Scalers
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Standard Programmable Video
Input Format
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ITU-R BT.656, 8-Bit 4:2:2 With
Embedded/Discrete Syncs
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DVI Transmitter up to 165M
pixels/second
TV output supporting graphics resolutions up to 1024 x768
pixels
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Support for all NTSC and PAL
formats on video output
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Provides CVBS, S-Video and
SCART (RGB) outputs
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4.HSMC DVI Board |
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Combined DVI input and output
board for Altera FPGA development kits with HSMC expansion
port.
HSMC DVI Board :
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Digital Visual Interface
Compliant (DVI 1.0)
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Supports resolutions from VGA
to UXGA (1600x1200 & 1920x1080)
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25 - 165 Mhz Pixel rates
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EDID data reading/writing
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Monitor detection through
Hot-Plug
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5.HSMC Prototyping board |
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Prototyping board for Altera
FPGA development kits with HSMC expansion port.
HSMC
Prototyping board :
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High quality, 4-layer, FR4 PCB
with plated thru holes
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Convenient access points to
every pin on the HSMC connector
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Plugs into Altera Stratix III
and Cyclone III development kits using the HSMC interface
standard
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6.IP Camera Front End |
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Altera optimised CMOS sensor
front end IP core.
IP Camera Front End :
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Fully parameterised line
buffer·
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Auto line length adaptation
for run-time resolution changes·
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Minimal memory footprint·
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Fully parameterised·
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Bayer to RGB conversion·
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Colour bar output·
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Gamma correction/Colour space
conversion
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其它Altera原廠開發工具的Santa
Cruz介面相容 |
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1.SC Camera interface |
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5.2 Mega pixel camera module for
the Altera FPGA development kits with Santa Cruz expansion
port.
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5.2 Megapixel Omnivision CMOS
sensor
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Resolution to 2,592x1,944
Nios II compatible
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2.SC DVI input |
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DVI input interface for Altera
FPGA development kits with Santa Cruz expansion port. Feed
real-time video into your FPGA designs!
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Digital Visual Interface
Compliant (DVI 1.0)
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Supports resolutions from VGA
to UXGA
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25 – 165 Mhz Pixel rates
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EDID data reading
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Monitor detection through
Hot-Plug
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3.SC DVI output |
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DVI output interface for Altera
FPGA development kits with Santa Cruz expansion port.
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Digital Visual Interface
Compliant (DVI 1.0)
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Supports resolutions from VGA
to UXGA
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25 – 165 Mhz Pixel rates
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EDID data reading
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Monitor detection through
Hot-Plug
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4.SC Prototyping board |
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Prototyping board for Altera
FPGA development kite with Santa Cruz expansion port.
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4 Layer PCB with convenient
0.1" pitch spacing hole.
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+3.3V, +5V and GND marked
access points
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Fan-out of Santa Cruz
Connectors
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Altera DE3 |
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Altera
DE3 最新多媒體平台
Altera Stratix III 3SL340 FPGA
with 338,000 LEs
DDR2 SO-DIMM Socket
SD Card Socket
Altera Serial Configuration
deivices (EPCS128) for Stratix III 3SL340
USB Blaster built-in for
programming and user API controlling
USB Host/Slave Controller with
one mini-AB for host/device and two type A for device
Eight 180-pin High Speed Terasic
Connectors ( HSTC )
Two 40-pin Expansion Headers
with diode protection
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Altera DE2-70 多媒體平台及數位 LCD 面板和相機套件組 |
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DE2-70多媒體數位平台榮獲 Altera美國總公司採購用於2006年四月全球嵌入式系統會議展出,並用於Altera
於全球大廠之多媒體應用展示, 本平台提供所有硬軟體及示範程式 (Verilog code)。 |
本套件包含:
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USB Blaster 下載 Cable |
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MAX II Micro Kit |
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