Applications: 

• Video surveillance system
• Security cameras
• Video monitoring system (process industry)
• Personal video recorder (Set-top box)
• Digital video recorder (Security systems)
• Video phones and video conferencing application
• Networked video application
• Video base station Imaging application
• 3-D graphics application

Technical Specifications

• Video Input Interface

• High quality single chip video decoder, which converts NTSC/PAL or S-video input to digital format

• Accepts NTSC(M) and PAL(B, D, G, H, I, M, N) composite video, S-video input

• Automatic detection of 50/60 Hz field frequency and automatic recognition of all common broadcast standards

• RCA Jack Connector for NTSC/PAL input and 4-Pin Mini DIN connector for S-video input

• Decoder Output

• 16-bit programmable digital video output in 4:2:2 or 4:1:1 format. Outputs are formatted according to ITU-R BT.601 standard or square pixel format

• Resolution Supported: NTSC: 352 X 288, 640 X 480, 720 X 480 / PAL: 352 X 288, 720 X 576, 768 X 576

• Video Output Interface

• High quality single chip video encoder which converts digital data into NTSC/PAL and S-video signal

• Provides NTSC(M) and PAL(B, D, G, H, I) composite video and S-video output simultaneously

• RCA Jack Connector for NTSC/PAL output and 4-Pin Mini DIN connector for S-Video output

• Encoder Input

• Resolution Supported: NTSC: 352 X 288, 640 X 480, 720 X 480 / PAL: 352 X 288, 720 X 576, 768 X 576

• Input format supported is 4:2:2 Interlaced as per ITU standard ITU-R BT.601

• Ethernet Interface

• High quality single chip Ethernet controller

• Fully integrated IEEE 802.3/ 802.3u-100Base-TX / 10Base-T Physical layer

• Supports full duplex switched Ethernet

• Supports 32 Bit asynchronous host interface

• Auto Negotiation: 10/100, Full/Half Duplex

• On chip wave shaping - no external filters required

• RJ45 Connector for Ethernet output

• FPGA

• High performance, 200 K usable gates, 56 Kbits RAM Xilinx Spartan-II Series FPGA

• FIFO for receive and transmit video is synthesized in FPGA

• Control/Status registers and all interface glue logic is incorporated in FPGA

• FPGA has about 50% free space to accommodate data manipulation algorithm such as Filtering, Compression, Decompression etc.

• DSP Interface 

• vDB has two expansion connectors compliant to TMS320 Cross-platform daughter board specifications V1.0 that allows it to be connected to the EVM board

• One expansion connector provides access to the DSP’s asynchronous external memory interface (EMIF) and the other to the on-chip peripheral and control/status signals

詳細資料請聯絡: tech@ict.com.tw