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Language
to Layout (A
Top-Down DSP Design Process Seminar ) |
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| 研討會簡介： |
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Pioneers
in EDA technologies present an exciting seminar on advances in DSP
design processes. Join us to learn how new synthesis tools now allow
DSP algorithm developers to quickly and effectively implement their
algorithms in field programmable gate arrays (FPGAs). AccelChip has
introduced the industry’s first high-level synthesis tool for the
MATLAB® language that automatically generates
optimized RTL models and simulation testbenches. APlus Technology
provides physical synthesis tools for automatic optimization of the
physical layout of FPGAs from RTL models. The combination of these
tools provides a highly efficient design process that lets DSP
designers go from language to layout in weeks, not months.
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| 研討會場次及地點： |
| 第一場： |
92年1月23日(AM8:30~AM
11:30) 資策會科技大樓簡報室 |
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地址：台北市和平東路2段108
號 台北捷運科技大樓站旁 |
| 第二場： |
92年1月23日(PM13:00~PM
16:00) 桃園中科院 龍園園區 |
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地址：園縣龍潭鄉高平村石崎子15號
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第三場： |
92年1月24日(AM8:30~AM
11:30) 國家高速電腦中心1樓多媒體教室 |
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地址：新竹市科學工業園區研發六路7號
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| 邀請對象： |
歡迎各級學校機關、研究單位及企業界單位來參與，研討會完全免 |
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費，
並提供相關資料。 |
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| 主辦單位： |
美國AccelChip,
Inc. |
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智控科技股份有限公司(Intelligent
Control Technology Co.,Ltd,) |
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| 活動議程：1 |
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第一、三場
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Session
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Topic
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Speaker
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08:30~08:50
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Registration
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08:50~09:00
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Introduction
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Jason
Chen, Manager ,ICT, Inc.
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09:00~09:50
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A
True Top-Down DSP Design Process
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Dan
Ganousis, President, AccelChip, Inc.
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09:50~10:40
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Physical
Synthesis for FPGA Design
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Jason
Cong, President, APlus Technology
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10:40~10:50
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Break
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10:50~11:40
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Language
to Layout DSP Design Demo
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Mark
Eslinger, Applications Engineering Manager, AccelChip,
Inc.
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11:40~12:00
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Questions
and Answer Session
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第二場
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Session
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Topic
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Speaker
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13:00~13:10
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Registration
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13:10~13:20
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Introduction
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Jason
Chen, Manager ,ICT, Inc.
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13:20~14:00
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A
True Top-Down DSP Design Process
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Dan
Ganousis, President, AccelChip, Inc.
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14:00~14:40
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Physical
Synthesis for FPGA Design
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Jason
Cong, President, APlus Technology
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14:40~14:50
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Break
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14:50~15:30
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Language
to Layout DSP Design Demo
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Mark
Eslinger, Applications Engineering Manager, AccelChip,
Inc.
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15:30~16:00
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Questions
and Answer Session
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現場會有智控科技展示"Aldec/Accelchip"操作及應用程式Demo |
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| 演解者的資料： |
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Dan
Ganousis is the President and CEO of
AccelChip, Inc located in Chicago, Illinois, USA. Previously
he has served as Vice President of Marketing at Mentor
Graphics and Viewlogic. An IC designer by education, Dan
worked on leading edge microprocessor design projects at
Solbourne Computer, Digital Equipment Corporation, NCR
Microelectronics, and Zilog Computer for the first 15 years of
his career. Dan holds a B.S.E.E. degree from Rensselaer
Polytechnic Institute in Troy, NY, USA.
Dr.
Jason Cong is the Founder, President and
CEO of APlus Design Technologies located in Los Angeles,
California, USA. Dr. Cong is a Professor at UCLA and is a
world-renowned, leading expert in the field of FPGA synthesis
and VLSI physical design. Dr. Cong led the development of the
UCLA RASP, a well known advanced FPGA synthesis system widely
used in the programmable logic industry and research
community. Dr. Cong is the co-chair of this year’s ASP-DAC
in Japan.
Mark
Eslinger
is the manager of the Field Applications Engineering group for
AccelChip, Inc. located in San Jose, California, USA. Mark
previously worked at Averant, Sequence Design, Abstract and
Synopsys in various technical roles. Mark started his career
as a hardware designer at Lockheed-Martin and holds an M.S.E.E.
degree from Santa Clara University and a B.S.E.E. degree from
Walla Walla College.
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