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Hyperception
SPEEDY-33 DSP
是有高效能表現並可在短時間內用直接的觀念完成信號處理的程式設計的獨立作業的硬體。可以輕易的把生活上許多重要類比信號處理的應用，使用德州儀器的
VC33 DSP
來完成。
SPEEDY-33 DSP
可以輕易的利用 Hyperception
圖形化 DSP
設計軟體 (VAB)
設計較高階的程式，這程式設計的環境可以設計、觀察、分析和執行來自
SPEEDY-33 DSP 所傳來的信號，而不用使用
C
語言或組合語言。
SPEEDY-33 DSP
規格描述：
High-Performance Floating-Point Digital
Signal Processor (DSP):
13-ns Instruction Cycle Time
150 Million Floating-Point Operations Per Second (MFLOPS)
75 Million Instructions Per Second (MIPS)
34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static
Random-Access Memory (SRAM)
Configured in 2 × 16K plus 2 × 1K Blocks to improve Internal
Performance
x5 Phase-Locked Loop (PLL) Clock Generator
Very Low Power: < 200 mW @ 150 MFLOPS
32-Bit High-Performance CPU
16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
4 Four Internally Decoded Page Strobes to Simplify Interface
to I/O and Memory Devices
Boot-Program Loader
EDGEMODE Selectable External Interrupts
32-Bit Instruction Word, 24-Bit Addresses
Eight Extended-Precision Registers
Fabricated Using the 0.18-um (leff-Effective Gate Length)
TImeline™ Technology by Texas
Instruments (TI)
On-Chip Memory-Mapped Peripherals:
One Serial Port
Two 32-Bit Timers
Direct Memory Access (DMA)
Coprocessor for Concurrent I/O and CPU Operation
164-Pin Low-Profile Quad Flatpack (HFG Suffix)
144-Pin Non-hermetic Ceramic Ball Grid Array (CBGA) (GNM
Suffix)
Two Address Generators With Eight Auxiliary Registers and Two
Auxiliary Register Arithmetic
Units (ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution
in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle Branches
Conditional Calls and Returns
Interlocked Instructions for Multiprocessing Support
Bus-Control Registers Configure Strobe-Control Wait-State
Generation
1.8-V (Core) and 3.3-V (I/O) Supply Voltages
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