The JTAG emulation technology communicates directly with the processor and lets data be moved on (and off) chip non-intrusively, without interrupting the code execution.

        This technology capability is augmented due to additional logic on the DSP target to provide even greater visibility and access into registers and other internal functions as on-chip cache memories.
Emulation provides user many levels of capabilities through Code Composer Studio (software development environment for TI's DSPs) that are :

• The debugger source code display: many of the most common debugging operations such as hardware breakpoints, watchpoints and counters are available via a single mouse click on a line of code.
• The Event analysis window: provides a single display of and control over all on-chip debug tasks.
• The benchmarking capability: helps developers to analyze their system performances and makes system-level tradeoffs by measuring different items, including elapsed cycles, branches, pipeline stalls, cache hits/misses, interrupts, DMA interrupts, and others.
• The Event Sequencer window: tracks down the most elusive of real time problems.

        Emulator and CCS allow user to see what is happening in the last moments before the embedded system is expected to fail. Without this tool, tracking down the intermittent real-time bugs will be a fastidious job due to the unknown state when the failure occured.

• PCI 32 bits 33 MHz rev 2.2: 3V3 / 5V compatible (universal PCI interface)

• DLL mode:Universal mode: compatible with Windows 98, NT4, 2000 & XP

• Legacy mode:Enhanced performance: compatible with Windows 2000* & XP*(* depends on the PC configuration)

• External pod:Link uses LVDS signaling

• JTAG clock frequency:5, 10, 20, 33* MHz(*Only with an internal emulation of the target board)

Download the aDICE data-sheet (PDF version)